Liquid crystal displays and like flat-panel displays have found use in a wide range of applications due to their thinness, low power consumption, and other advantages. Besides, in recent years, there are increasing demands for liquid crystal projectors as high-definition displays used in presentation, home theaters, and other situations. In many such projectors, the liquid crystal display is used as a light bulb.
A typical liquid crystal display has liquid crystal sandwiched between an active matrix substrate and an opposite substrate. On the active matrix substrate are there provided signal lines and scan lines crossing each other, as well as pixel electrodes and switching devices, etc. at the respective intersections of the signal and scan lines to control the writing of a signal to the pixel electrodes. On the opposite substrate is there formed an opposite electrode which is commonly shared among all the pixels. To improve the aperture ratio of the liquid crystal display, an interlayer insulating film is provided to cover the plane on which the signal and scan lines are formed, and the pixel electrodes are formed on that interlayer insulating film. The structure allows the pixel electrodes to overlap the signal and scan lines and cover a large area, thereby increasing the aperture ratio. The switching device is in many cases a TFT (thin film transistor).
The TFT leaks current upon light exposure, which is a unique disadvantage to the TFT. In liquid crystal displays, the photo-induced leak current results in poor contrast and increased crosstalk which in turn cause poor display quality. The problems are particularly serious with liquid crystal displays in liquid crystal projectors in which the display is used under intense light.
To solve the problems, in other words, to restrain the photoleak current, in conventional structures, a light-shield film or layer made of a metal or other material is provided at a level above the TFTs and below pixel electrodes.
In such structures, wires, TFTs, and other components are formed below the light-shield film. In other words, the light-shield film is provided on an underlying surface which is irregular due to the wires, TFTs, etc. and is thin at slopes on the irregular surface. The light-shield film thus cannot exhibit its full light-shielding potential.
In the light-shield film structure, the pixel electrodes of course sit on irregularities due to the light-shield film on which the electrodes are deposited, as well as those irregularities due to wires, TFTs, etc. The pixel electrodes are topped by an alignment film which is subjected to alignment treatment so as to align the liquid crystal molecules in a predetermined direction. The existence of irregularities is however a hindrance for a proper alignment treatment to be carried out where the irregularities cause abrupt changes in surface level. The result is defective alignment of the liquid crystal. Another problem arises if those parts where alignment is defective are shielded against light to ensure a good contrast level: the aperture ratio, and hence brightness, drops dramatically, especially in liquid crystal displays for the liquid crystal projector with small pixels.
Various suggestions have been made about planarization structure to address these problems caused by underlying surface irregularities. Japanese Unexamined Patent Application, or Tokukai, 2001-242443 published on Sep. 7, 2001 is an example.
FIG. 13 shows a liquid crystal display disclosed in the Application. The liquid crystal display in FIG. 13 is one with planarized films (planarization films), a first planarization film 131 filling the surface irregularities due to thin film transistors, a second planarization film 130 filling the surface irregularities due to the light-shield film 109.
The first and second planarization films 130, 131 are fabricated by either planarizing the surface of a deposited insulating film by chemical mechanical polishing (CMP) or spin-coating the underlying surface flatly with an insulating material which is then baked (SOG).
Now, referring to FIG. 13, the following will briefly discuss a method of manufacturing the liquid crystal display disclosed in the Application. First, a film of polycrystalline silicon (Si) doped with phosphorous (P) and a tungustenic silicon (WSi) film are deposited in this order on a silicon dioxide glass substrate 113. The films are then patterned into a light-shield film 112.
Next, a silicon dioxide (SiO2) interlayer insulating film 107b and a polycrystalline silicon film are deposited in this order covering the entire substrate surface by, for example, chemical vapor deposition (CVD). The latter film is patterned into a polycrystalline silicon film (polycrystalline Si film) 114.
Thereafter, a silicon dioxide (SiO2) gate insulating film 117 is deposited covering the entire substrate surface by, for example, CVD. Subsequently, the films sequentially formed covering the entire substrate surface, for example, the P-doped polycrystalline Si film and the WSi film, are patterned into gate wires 116 and electrodes 115 which will be used for additional capacitance elements.
A SiO2 interlayer insulating film 107a is then deposited covering the entire substrate surface by, for example, CVD. The interlayer insulating film 107a and the gate insulating film 117 are partly etched away where specified to form contact holes 111a. 
Next, either a WSi film or an aluminum (Al) film and WSi film are deposited covering the entire substrate surface and patterned into lead electrodes 110 and signal wires 120.
Then, a SiO2 interlayer insulating film (not shown) is deposited covering the entire substrate surface by, for example, atmospheric pressure CVD. Next, a silicon nitride (SiN) film (not shown) is deposited covering the entire substrate surface by, for example, plasma CVD and patterned.
Next, a SiO2 film is deposited covering the entire substrate surface by, for example, plasma CVD using TEOS as a source gas. The film is polished by, for example, CMP to form the first planarization film 131. The Application discloses an example in which the film, 2500 nm thick prior to the polishing, is polished down to 2200 nm by CMP so that the film has a smooth surface. The CMP process is capable of reducing remaining surface steps to 0.5 μm or less and, depending on conditions, even to 0.1 μm or less.
Next, the first planarization film 131 and an interlayer insulating film (not shown) are partly etched away where specified to form contact holes 111b. A titanium (Ti) film is then deposited covering the entire substrate surface by, for example, for example, vapor deposition or sputtering and patterned into a electrically conductive light-shield film 109.
Next, the second planarization film 130 is formed on the light-shield film 109 with an intermediate film (not shown) intervening there between. The intermediate film is, for example, a SiO film made by plasma CVD using TEOS as a source gas. The second planarization film 130 is formed on that intermediate film by SOG. Alternatively, the second planarization film 130 may be formed by CMP.
Next, the second planarization film 130 is partly etched away where specified to form contact holes 111c. An ITO film of a for example, 70-nm thickness is then deposited covering the entire substrate surface and patterned into pixel electrodes 106. Thereafter, an alignment film 105 is formed on the pixel electrodes 106 and subjected to alignment treatment, which concludes the fabrication of an active matrix substrate 201.
An opposite substrate is fabricated by sequentially forming on the silicon dioxide glass 113 an alignment film 103 and an opposite electrode 102 of a transparent, electrically conductive film and subjecting the alignment film 103 to alignment treatment. The active matrix substrate 201 fabricated as above and the opposite substrate are combined so that the alignment films 105, 103 are located opposite each other. A liquid crystal layer 104 is sealed between the substrates, which concludes the fabrication of a liquid crystal display.
However, in a method disclosed in the Application for forming the first and second planarization films 131, 130 whereby CMP is used to polish films, deposited on irregular surfaces, which will become the first and second planarization films 131, 130 so that they have flat surfaces, the films which will be polished are thicker by far than films deposited in a film formation step and portions etched away in an etching step in ordinary manufacture of a liquid crystal display. Further, the portion polished and hence removed by CMP needs to be thicker than the steps on the underlying surface and hence thicker by far than films deposited in a film formation step and portions etched away in an etching step in ordinary manufacture of a liquid crystal display. Note that the thickness of that portion polished and removed by CMP will be referred to as the “polishing amount.”
For example, as shown in FIGS. 14(a) to 14(d), to form the first planarization film 131 by CMP, the thickness of the SiO2 film 140 to be polished and the thickness of the portion 141 polished and hence removed by CMP (polishing amount) need to be greater than X, or the depths of the steps on the underlying surface. In the case of the first planarization film 131, a specific example disclosed in the Application, the film 140 to be polished is 2500 nm in thickness, and the portion 141 polished and hence removed by CMP is 2200 nm in thickness.
A film is required that is far thicker than a film deposited in a film formation step and a film etched away in an etching step in ordinary manufacture of a liquid crystal display. In a film planarization process by CMP, the greater the depths X of the steps on the underlying surface, the thicker the film 140 to be polished and the portion 141 polished and hence removed by CMP.
In the manufacture of a liquid crystal display, there is a minimum level of uniformity in thickness required of polished films. In other words, variations in thickness of polished films need to be brought within a certain level. It is difficult to keep uniform the thickness of the polished film 140 if the film 140 before polishing is thick and the portion 141 which will be polished and hence removed is also thick for the foregoing reasons. A specific problem arises, in bringing the variations within a certain, restricted range: requirements are extremely high as to both the uniformity in thickness of the polished film 140 and the uniformity in thickness of the portion 141 polished and hence removed by CMP.
Assuming that the film 140 to be polished is 2500 nm in thickness and also that the portion 141 polished and hence removed by CMP is 2200 nm in thickness, an example will be given below showing an attempt to restrict the variations in thickness of the polished film 140 within ±15%, or 300±45 nm. For convenience in description, it is further assumed that the polished film 140 and the portion 141 polished and hence removed by CMP have the same variations in thickness: that is, the polished film 140 is 2500±Δ nm in thickness, and the portion 141 polished and hence removed by CMP is 2200±Δ nm in thickness. Under these conditions, (Δ2+Δ2)1/2≦45 nm. Solving the inequality for Δ, we obtain Δ≦32 nm.
Based on the value of Δ, the uniformity in thickness of the polished film 140 and the uniformity in thickness of the portion 141 polished and hence removed by CMP which restrict the variations in thickness of the polished film 140 within ±15% are obtained as in the following. The uniformity in thickness of the polished film 140 needs to be (Δ/2500)·100=(32/2500)·100=1.3%. The uniformity in thickness of the portion 141 polished and hence removed by CMP needs to be (Δ/2200)·100=(32/2200)·100=1.5%. In other words, in conventional methods, to restrict the variations in thickness of the polished film within ±15% (300±45 nm), both the uniformity in thickness of the polished film 140 and the uniformity in thickness of the portion 141 polished and hence removed by CMP need to be within 1.5%.
These requirements for excellent uniformity, i.e., such strict restrictions on the uniformity in the thickness of the polished film 140 and the uniformity in thickness of the portion 141 polished and hence removed by CMP that they fall within 1.5% as discussed here, presents a major obstacle in mass-producing liquid crystal displays.
Note that although these problems are unique to CMP and do not occur in SOG as a film planarization method, SOG has its own problems: the method is capable of smoothing out steps on the underlying surface only partially, not completely and not much reliable in a high intensity light environment, as when applied to projector panels, because of possible light-induced chemical reactions of an organic component leftover from the SOG process. The present invention does not consider SOG and instead focuses on the formation of a planarization film based on CMP which is free from these problems.